1. Field of the Invention
This invention concerns a current mirror circuit. More particularly, this invention concerns a current mirror circuit which is operative at a relatively low power source voltage.
2. Description of the Prior Art
A current mirror circuit is widely used as a basic circuit, such as a constant current source for a bias circuit, or as a current distribution circuit in an analog circuit, as well as an amplifier circuit.
FIG. 1A and FIG. 1B are circuit diagrams of basic current mirror circuits.
In FIG. 1A, the emitter electrodes of PNP transistors Q1 and Q2 are connected to a power source terminal Vcc, and the base electrodes thereof are connected in common. The common connection of the base electrodes of the transistors Q1 and Q2 is connected to a ground terminal GND through an input current source 1. The collector electrode of the transistor Q2 is connected to the GND terminal.
In this circuit, when the transistors Q1 and Q2 have same geometric dimension, the collector current Is of the transistor Q2 is equal to the input current Iref, assuming that the base currents of the transistor Q1 and Q2 are negligible with respect to the collector currents of the transistors Q1 and Q2. This current mirror circuit is operative at a power source voltage which is higher than the base-emitter voltage VF of the transistors Q1 and Q2.
However, in this circuit, as the base currents of the transistors Q1 and Q2 are added to the collector current of the transistor Q1, this causes an error in the current mirror ratio between the input current Iref and the collector current Is of the transistor Q2. Namely, the relationship between the input current Iref and the output current Is is expressed as follows: ##EQU1## wherein h.sub.FE is the current gain of the transistors Q1 and Q2. Assuming that the h.sub.FE is 10, the output curent Is is approximately about 0.83.Iref from equation (1). This error is notable when the current gains of the transistors Q1 and Q2 are low. Thus, the collector current Is of the transistor Q2 decreases compared with the input current Iref, as shown in FIG. 2 as a dotted line, when the current gain is low.
In FIG. 1B, NPN transistors are used instead of the PNP transistors in the circuit of FIG. 1A. The common base connection of the transistors Q3 and Q4 is connected to the collector electrode of the transistor Q3 in the same way as in FIG. 1A. Thus, the same problem exists in this circuit.
To solve the above problem, improved current mirror circuits as shown in FIGS. 3A and 3B have been used.
In the circuit of FIG. 3A, a compensating transistor Q5 of PNP type is provided. Namely, the emitter electrode of the transistor Q5 is connected to the common connection of the base electrodes of the transistors Q1 and Q2. The base electrode of the transistor Q5 is connected to the collector electrode of the transistor Q1, and the collector electrode thereof is connected to the GND terminal.
In this circuit, the current to be added to the collector current of the transistor Q1 is reduced to 1/h.sub.FE of the base currents of the transistors Q1 and Q2 (h.sub.FE is the current gain of the transistor Q5). The relationship between the output current Is and the input current Iref can be expressed as follows: ##EQU2## Assuming that the h.sub.FE is 10, the Is is approximately 0.98.Iref. Thus, the error of the current mirror ratio due to the base current is improved.
In the same way, the current mirror circuit of FIG. 3B is provided with a compensating transistor Q6 of NPN type to improve the current mirror ratio thereof.
However, in these current mirror circuits, it is necessary to increase the power source voltage higher than 2 VF to operate the circuits. Thus, the minimum power source voltage to operate the current mirror circuit is increased to 2 VF as shown in FIG. 4.